1. Field of the Invention
This invention relates to a semiconductor device, and more particularly, to a package technique of a semiconductor chip.
2. Description of Related Art
At present, in semiconductor devices, high capacity and high speed are pursued and simultaneously a size of a package substrate is downsized. Dynamic random access memories (DRAMs) are used as high-performance memories in various uses such as a cellular telephone, a server, a personal computer (PC), or the like. Therefore, small species and high volume production are desired in the DRAMs. Accordingly, the DRAM chip which is operable, as one chip, at different data width of four, eight, sixteen, thirty-two, and so on is developed. Such a DRAM chip can be configured to perform data read ant write operations in one of 4-bit, 8-bit, 16-bit, and 32-bit units which will later be also described as a X4 product (a X4 device), a X8 product (a X8 device), a X16 product (a X16 device), and a X32 product (a X32 device), respectively. A general product is standardized by organization called Joint Electronic Device Engineering Council (JEDEC). In this spec, a pin configuration of the package substrate, pin signal assignment, and so on are defined in accordance with the DRAM chip and the data width thereof.
JP-A-2007-95911 (which corresponds to US Patent Application Publication No. US 2007/0085214 A1) discloses a semiconductor device having a semiconductor chip which is usable as any one of 4-bit, 8-bit, and 16-bit structure devices (X4, X8, and X16 products), and a package substrate for packaging the semiconductor chip. The semiconductor chip has first and second DQ pad groups of DQ system pads for the 16-bit structure device (the X16 product). The first DQ pad group is arranged in a first area at a vicinity of a middle part of a surface of the semiconductor chip while the second DQ pad group is arranged in a second are at an outer side of the first area on the surface. An additional pad necessary as one of DQ system pads for the 8-bit structure device (the X8 product) except for pads included in the second DQ pad group is formed in the second area. The additional pad is used on operating the semiconductor device as the 4-bit structure device (the X4 product) or the 8-bit structure device (the X8 product). That is, by adding the additional pad, JP-A-2007-95911 obtains the semiconductor device which is configured to perform data read and write operations in one of 4-bit, 8-bit, and 16-bit units. The semiconductor device disclosed in JP-A-2007-95911 is based on the premise that it is used as a SDRAM chip of a DDR3 type and JP-A-2007-95911 neither describes a SDRAM chip of a DDR2 type. Inasmuch as the pin configuration of the package substrate and the pin signal assignment are absolutely different between the SDRAM chip of the DDR2 type and the SDRAM chip of the DDR3 type, consideration different from that in the SDRAM chip of the DDR3 type is required in the SDRAM chip of the DDR2 type.
In the manner which is described above, the pin configuration and the pin signal assignment are different caused by the semiconductor memory chips and types of data widths thereof. In addition, in order to configure different bit configuration products at the same chip, a chip size is increased because exclusive chip pads are required.